About Me
I am doing my MS in the field of Computer Architecture and VLSI (CS), under the guidance of Dr. V Kamakoti. Also working with Dr. Srinivasan Murali, CTO of iNoCs and who is also a research scientist at EPFL.
Current Research
Currently, my research focus is in the area of Network-on-Chip (NoC). In the present Multicore and advanced embedded systems era,
more and more components find their way into a chip to meet the high computational requirements. This, however has a huge impact
on the communication architecture of the chip. No more will the traditional shared bus, point-to-point wiring suffice. Hence there
is a need for a better communication architecture.
NoC is a highly structured, modular and scalable design of a communication architecture that can meet the huge demands of today.
My research focus is on sizing the buffers in the NoC, thus optimizing its power and area budget. Also working on 3D chips.
Courses
- Computer Architecture
- Digital Design and Verification
- Performance Evaluation of Computer System
- Mathematical Concepts for Computer Science
- Advanced Data Structures and Algorithms
Projects
- Formal Verification of Safety Critical circuits for IGCAR
- Design and Verification of ESI cache model
- Design and Verification of simple 4X4 Network on Chip router
- PODEM: An ATPG Tool
Publications
[1] Anish S Kumar, M Pawan Kumar, Srinivasan Murali, V Kamakoti, Luca Benini, Giovanni De Micheli; A Simulation based Buffer Sizing Algorithm for Network on Chip; To be Communicated.